By John L. Henning (auth.), David Kaeli, Kai Sachs (eds.)
This e-book constitutes the lawsuits of the SPEC Benchmark Workshop 2009 held in Austin, Texas, united states on January twenty fifth, 2009.
The nine papers provided have been conscientiously chosen and reviewed for inclusion within the ebook. the result's a suite of top quality papers discussing present concerns within the sector of benchmarking learn and expertise. the themes coated are: benchmark suites, CPU benchmarking, power/thermal benchmarking, and modeling and sampling strategies.
Read or Download Computer Performance Evaluation and Benchmarking: SPEC Benchmark Workshop 2009, Austin, TX, USA, January 25, 2009. Proceedings PDF
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This publication constitutes the complaints of the SPEC Benchmark Workshop 2009 held in Austin, Texas, united states on January twenty fifth, 2009. The nine papers awarded have been conscientiously chosen and reviewed for inclusion within the publication. the result's a suite of high quality papers discussing present concerns within the quarter of benchmarking study and know-how.
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Additional resources for Computer Performance Evaluation and Benchmarking: SPEC Benchmark Workshop 2009, Austin, TX, USA, January 25, 2009. Proceedings
Hoﬂehner2 , Arun Kejariwal1 , Daniel M. Lavery2, Alexandru Nicolau1 , Alexander V. Veidenbaum1 , and Cameron McNairy2 1 Center for Embedded Computer Systems University of California, Irvine Irvine, CA 92697, USA 2 Intel Compiler Lab Intel Corporation Santa Clara, CA 95050, USA Abstract. This paper presents the performance characteristics of the Intel R Itanium R 2-based Montecito processor and compares its performance to the previous generation Madison processor. Measurements on both are done using the industry-standard SPEC CPU2006 benchmarks.
Desai et al. GemsFDTD, we observe that the number of L2D cache misses is higher than L1D cache misses. This stems from the fact that in Itanium ﬂoating-point loads do not access the L1D. The beneﬁt of this is that it enables the issue of ﬂoating-point loads on any of the 4 memory ports with minimal restrictions. It also explains the higher L2D and L3 data cache miss rate in CFP2006 as compared to CINT2006. For example, CFP2006 incurs over 2-fold L3 data cache misses compared to CINT2006. This in turn increases the memory bus pressure thereby aﬀecting performance adversely.
Contrary to intuition, we note that the number of L2DTLB misses is higher than L1DTLB misses in CFP2006. This stems from the fact that in Montecito ﬂoating-point memory operations bypass the L1DTLB and access the L2DTLB directly (for details see page 94 in ). This corresponds to an increase in hardware page walker utilization which may aﬀect performance adversely. Use of larger pages (> 16 KB) for data can potentially mitigate the above in such cases. xalancbmk. zeusmp incur a small cache miss rate; likewise the branch prediction rate is also negligible.
Computer Performance Evaluation and Benchmarking: SPEC Benchmark Workshop 2009, Austin, TX, USA, January 25, 2009. Proceedings by John L. Henning (auth.), David Kaeli, Kai Sachs (eds.)